The invention relates generally to sequential digital circuits and, more particularly, to clocked flip flop circuits.
Digital data processing systems (e.g., computer systems) commonly employ bus structures to provide data communication between functional units within the system. For example, a computer will generally include a front-side bus to provide communication between the main processor and the chip set of the computer. The bus will typically include a data transmission medium that extends between two (or more) functional units. The bus can also include a transmission medium for carrying a clock signal between the units (such as in systems using source synchronous timing). A driver within one of the functional units is used to transmit a data signal onto the data transmission medium toward the other functional unit. A receiver within the other functional unit receives the data signal from the transmission medium, detects the data within the signal (e.g., using the associated clock signal), and temporarily stores the detected data. The data can then be used by processing functionality within the second functional unit. The speed with which the receiver can receive data from the transmission medium (i.e., the setup and hold time of the receiver) will typically dictate the maximum speed of the bus. It is generally desirable that data busses operate as quickly as possible, so receivers having low setup and hold times are desired. As a significant amount of noise may be present in the vicinity of a data processing system, it is also generally desirable that bus receivers operate in a relatively robust manner in the face of such noise.